(1) Field of the Invention
This invention relates to a method of fabrication in the formation of an improved copper metal diffusion barrier layer, W/WSiN/WN, by a combination of a tungsten nitride bottom layer, followed by an in situ silane soak process forming a WSiN layer, and a final top layer of tungsten, in single and dual damascene interconnect trench/contact via processing with 0.10 micron nodes for MOSFET and CMOS applications.
(2) Description of Related Art
Related patents and relevant literature now follow as Prior Art.
U.S. Pat. No. 6,001,415 entitled xe2x80x9cVia With Barrier Layer for Impeding Diffusion of Conductive Material from Via Into Insulatorxe2x80x9d granted Dec. 14, 1999 to Nogarni et al. describes a method of forming various diffusion barrier layers, i.e., both pure WSiN and pure WN barrier layers, for conducting copper contact vias. The via structure described includes a barrier layer disposed between a via plug and an insulating layer surrounding a via hole to impede diffusion of conductive material from the via plug into the insulating layer. The deposition of the barrier metals described use an ion metal plasma sputtering process that is combined with a plasma etching process to remove unwanted barrier layer material from the bottom of the contact via.
U.S. Pat. No. 5,801,098 entitled xe2x80x9cMethod of Decreasing Resistivity in an Electrically Conductive Layerxe2x80x9d granted Sep. 1, 1998 to Fiordalice et al. describes a method of decreasing resistivity in an electrically conductive, diffusion barrier layer of TiN, that includes the use of a high density plasma sputtering technique to deposit the electrically conductive TiN layer. The electrically conductive diffusion barrier layer is further exposed to a plasma anneal.
U.S. Pat. No. 5,968,333 entitled xe2x80x9cMethod of Electroplating a Copper or Copper Alloy Interconnectxe2x80x9d granted Oct. 19, 1999 to Nogami et al. describes a process whereby copper or a copper alloy is electroplated to fill via/contact holes and/or trenches in a dielectric layer. A barrier layer is initially deposited on the dielectric layer lining the hole/trench. A thin conformal layer of copper or a copper alloy is sputter deposited on the barrier layer outside the hole/trench. Copper or a copper alloy is then electroplated on the conformal copper or copper alloy layer filling the hole/trench. During electroplating, the barrier layer functions as a seed layer within the hole/trench. The barrier layer materials include single layers of: W, WN, WSiN, TiN, TiSiN and TiW.
U.S. Pat. No. 5,907,188 entitled xe2x80x9cSemiconductor Device with Conductive Oxidation Preventing Film and Method for Manufacturing the Samexe2x80x9d granted May 25, 1999 to Nakajima et al. describes a semiconductor device that includes a semiconductor substrate, and a laminated film insulatively formed over the semiconductor substrate. A conductive oxidation preventing film is disposed between a refractory metal film and a semiconductor film, to prevent oxidation of the semiconductor film. Oxidation and diffusion barriers, i.e., single layers of W, WN, and WSiN, are mentioned in the specifications.
U.S. Pat. No. 5,985,762 entitled xe2x80x9cMethod of Forming a Self-Aligned Copper Diffusion Barrier in Viasxe2x80x9d granted Nov. 16, 1999 to Geffken et al. describes a process whereby a copper diffusion barrier is formed on the side walls of vias connected to copper conductors, to prevent copper diffusion into inter-level dielectric. A thin film of copper diffusion barrier material is deposited on the wafer post via etch. A sputter etch is performed to remove barrier material from the base of via and to remove copper oxide from the copper conductor. The barrier material is not removed from the sidewall during the sputter etch. Thus, a barrier to re-deposited copper is formed on the via sidewalls to prevent copper poisoning of the dielectric. Barrier materials that are mentioned include single layers of: Ta, TiN, Si3N4, TaN, WN, WSiN, and TaSiN.
It is a general object of the present invention to provide an improved method of fabrication in the formation of an improved copper metal diffusion barrier layer having the structure, W/WSiN/WN, in single and dual damascene interconnect trench/contact via processing with 0.10 micron nodes for MOSFET and CMOS applications. The diffusion barrier is formed by depositing a tungsten nitride bottom layer, followed by an in situ SiH4/NH3 or SiH4/H2 soak forming a WSiN layer, and depositing a final top layer of tungsten. This invention is used to manufacture reliable metal interconnects and contact vias in the fabrication of MOSFET and CMOS devices for both logic and memory applications and the copper diffusion barrier formed, W/WSiN/WN, passes a stringent barrier thermal reliability test at 400xc2x0 C. Pure single barrier layers, i.e., single layer WN, exhibit copper punch through or copper spiking during the stringent barrier thermal reliability test at 400xc2x0 C.
In summary of the present invention, a process flow description follows that summarizes the necessary process steps and sequence of steps necessary for the main embodiments of the present invention, to form W/WSiN/WN barrier layer, which exhibits high diffusion resistance to both copper and silicon (at both interfaces). The necessary process steps and sequence of steps necessary to form the W/WSiN/WN are outlined, as follows. Step one is the deposition of the WN film or layer in the trench/via opening by metal-organic chemical vapor deposition (MOCVD) from the reduction of tungsten organic precursors, or deposited by plasma-enhanced chemical vapor deposition (PECVD), or by physical vapor deposition (PVD), sputtering. Step two in the process flow description is the an in situ soak process treating the WN layer with a SiH4/NH3 gas mixture or a SiH4/H2 gas mixture, at between from about 300 to 400xc2x0 C. This reactive soak process forms a WSiN layer on top of the WN layer, thus a WSiN/WN barrier. Following the silane soak treatment, is step three, the final top barrier deposition by chemical vapor deposition (CVD) or physical vapor deposition (PVD), sputtering, of a tungsten layer. Thus, a W/WSiN/WN barrier layer is formed. Next, step four is the copper seed layer deposition with improved adhesion and copper crystal texture, preferred dense  less than 111 greater than , upon the rigid diffusion the barrier layer, W/WSiN/WN. This fine crystal texture is important for subsequent electrochemical deposition (ECD) of copper, which subsequently fills the trench/via cavity. The copper seed layer, deposited over the tungsten layer, exhibits fine, highly dense grains, as studied by scanning electron microscopy (SEM). The subsequent process step, the electrochemical deposition (ECD) of copper, is used to fill the trench cavity, upon the copper seed layer. The kinetics of the electrochemical copper deposition process are based on a uniform, defect-free seed layer and barrier layer with good adhesion properties. The underlying layers improve and make wider the process window for the deposition of copper to fill both single and dual damascene structures.
The final processing step in building of the single and dual damascene structure is the chemical mechanical polishing (CMP) back of the excess electrochemical deposited copper metal. The copper is chem-mech polished back without dishing. In addition, any excess seed layer and barrier layer are removed from the top substrate surface. The copper is polished back so that only the copper that lies in the openings is left to form single and dual inlaid structures that include via and interconnect portions. Device applications include MOSFET and CMOS devices.
This invention has been summarized above and described with reference to the preferred embodiments. Some processing details have been omitted and are understood by those skilled in the art. More details of this invention are stated in the xe2x80x9cDESCRIPTION OF THE PREFERRED EMBODIMENTSxe2x80x9d section.